If you want to perform an 8-bit or a 16-bit shift, you can do it in one instruction. There’s also a SL instruction which operates exactly the same as RLC except that it shifts a 0 in on the right, instead of the carry bit. The carry value shifts in to the least significant bit, the other 7 bits shift up, and the most-significant bit of the original byte shifts out into the carry bit.Īnother way of looking at this is to blur the “before” and “after” situations and instead emphasize the “rotate” part of Rotate Left through Carry: RLC.B operates on a byte stored somewhere (either a working register or a memory location), and on the carry bit in the chip’s status register. The only reason I’m showing 8 bits here is that it’s a little easier on the eyes than a 16-bit register. To be more pedantic: the dsPIC is a 16-bit architecture, but most of its instructions can operate on 16-bit words or 8-bit bytes an 8-bit rotate is RLC.B, whereas the default RLC operates on a 16-bit register. I’ve labeled this RLC which stands for Rotate Left through Carry, which is an instruction on the dsPIC architecture. This diagram shows an 8-bit byte before and after a shift operation. Most processors have some kind of shift-left and shift-right instructions, and what they do is, um, shift bits left or right. Since this is a shift register, we have to understand how to perform a shift. (Never mind the nuances for now, I’ll come back to this later.) I should say that I hate writing assembly… except in snippets for cases like this, and I don’t actually write the assembly completely, I let the compiler do it for me. Let’s look at implementing an LFSR at a very low level: assembly language! LFSR Updates in Assembly Such a large assembly implementation wasn’t what I expected here, and perhaps we should try rewriting it. There are a few other quirks, like interaction with chip special function registers taking 2 cycles rather than one, but if you’re just interacting with the 16 W registers and RAM, all the basic instructions take one cycle each.) (A conditional branch takes one instruction and acts as a NOP if not taken, but if there is a branch, it takes 4 cycles. What we care about is the code for lfsr_step there’s a lot going on there! Excluding the return, we’ve got 27 instructions that take 29 cycles worst-case mov.d is a double-word move that takes two cycles, and all the other instructions take one cycle each, except for branches and jumps if taken. The efficiency of the lfsr_init function doesn’t matter much to us, since it will just be called once.
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